1. Field of the Invention
The present invention relates to bar graph decoders outputting a thermometer code changing continuously at a constant ratio in response to a digital input signal, and more particularly, to a bar graph decoder configured of a simple logic gate.
2. Description of the Background Art
A D/A converter converting a digital signal into an analog signal is indispensable in the field of commercial electronic appliances for measurement, control, communication and the like. A D/A conversion technique often used generally includes a weighted resistance method and a method of dividing voltage by resistance. These two methods will be described briefly hereinafter.
First, the weighted resistance method will be described. FIG. 13 is a schematic diagram showing a configuration of a D/A converter according to the weighted resistance method. Referring to FIG. 13, the D/A converter according to the weighted resistance method includes n pairs S.sub.O to S.sub.n-1 for switching each formed of a p channel transistor and an n channel transistor and provided for each bit to which input is supplied, and resistors R.sub.o to R.sub.n-1 connected thereto and each having a resistance value with a binary weight. The D/A converter further includes a reference voltage supplying terminal 51 connected to a resistance network by switches S.sub.0 to S.sub.n-1 turning on and off for supplying a reference voltage VR, and an element 52 such as an operational amplifier collecting current flowing through the resistance network in order to generate a signal in proportion to a digital input.
Operation of the D/A converter will now be described. In response to n-bit digital input signals a.sub.0 to a.sub.n-1, switches S.sub.O to S.sub.n-1 are turned on and off. If input signal a.sub.0 is "1" for example, the n channel transistor is turned on, and there is a current flow of VR/r through resistor R.sub.0. If input signal a.sub.0 is "0", the p channel transistor is turned on, and there is no current flow through resistor R.sub.0. As to the state of a switch Si, it may be considered that switch Si is connected to VR when ai=1, and that switch Si is grounded when ai=0. Therefore, a sum I of current flows through resistors R.sub.0 to R.sub.n-1 is:
I=(a0/r+a1/2r+a2/2.sup.2 r+a3/2.sup.3 r+. . . +an-1/2.sup.n-1 r)=VR.SIGMA.ai/r.sup.i
An output voltage VO of an operational amplifier is: EQU VO=I.multidot.(-r/2)=-VR.SIGMA.ai.multidot.2.sup.-i.
Therefore, this circuit operates as the D/A converter.
Operation will now be described of the method of dividing voltage by resistance. When configuring the D/A converter, it is possible to obtain a thermometer code also by preparing 2.sup.n-1 voltages which satisfy Vi=i.multidot.LSB and selecting one of the voltages. FIG. 14 is a schematic diagram showing a configuration of a 3-bit D/A converter using such a method of dividing voltage by resistance. Referring to FIG. 14, by connecting eight (2i=2.sup.3 =8) identical resistors r in series, connection points of respective resistors (portions indicated by arrows in FIG. 14) apparently correspond to respective digital inputs, and the voltages thereof are 0, 1LSB, 2LSB, . . . 2.sup.n-1 LSB (MSB). Therefore, by decoding the digital input signal and turning on one of switches SW.sub.0 to SW.sub.n-1 provided at the connection points of respective resistors, an analog output can be obtained accordingly. In the example shown in FIG. 14, an output of (5/8) VR can be obtained with respect to digital input "101".
In the method of dividing voltage by resistance, a bar graph decoder 53 generating a signal turning on and off switches S.sub.0 to S.sub.n-1 in response to the n-bit digital input (A.sub.n-1, . . . A.sub.1, A.sub.0) is provided in addition to operational amplifier 52 described with respect to the weighted resistance method.
As described above, bar graph decoder 53 is a necessary circuit for turning on and off switches SW.sub.0 to SW.sub.n-1 in configuring the D/A converter using the method of dividing voltage by resistance. Bar graph decoder 53 in the above described D/A converter selects only an arbitrary switch among a plurality of switches. Description will now be given of a bar graph decoder which outputs a thermometer code corresponding to an input signal.
First, a 3-bit bar graph decoder which can be configured of simple logic and composite gates will be described as a conventional bar graph decoder with reference to FIG. 15. FIG. 15A is a schematic diagram showing a configuration of the 3-bit bar graph decoder, and FIG. 15B is a diagram showing data input to the bar graph decoder and data output therefrom.
Referring to FIG. 15A, a conventional bar graph decoder 101 includes input terminals 1c to 1e to which digital data (B3, B2, B1) are input, a logic circuit unit 100 connected to input terminals 1c to 1e and preparing switch select signals for obtaining an output signal corresponding to the input data, and output terminals 101a to 101g connected to logic circuit unit 100 and outputting switch select signals SEL1 to SEL7. Logic circuit unit 100 includes a 3-input OR circuit 100a, a 2-input OR circuit 100b, and a 2-input AND-2-input OR circuit 100c, a 2-input OR-2-input AND circuit 100d, a 2-input AND circuit 100e, and a 3-input AND circuit 100f, each of which is connected to necessary ones of input terminals 1c to 1e. Operation of bar graph decoder 101 will now be described. Referring to FIG. 15B, any of "000" to "111" is input to digital input terminals 1c (MSB) to 1e (LSB), the input data is converted in logic circuit unit 100 according to the digital input, and SEL1 to SEL7 which are switch select signals continuously output enable signals of the above described switches S.sub.0 to S.sub.n-1 or the like. When "000 (=0 in decimal numeral)" is input for example, all logic gates and composite gates output "0". Therefore, seven output terminals 101a to 101g all output "0". Then, when "001 (=1)" is input, only 3-input OR circuit 100a outputs "1". Therefore, only switch select signal SEL1 attains "1". Further, when "010 (=2)" is input, 3-input OR circuit 100a and 2-input OR circuit 100b output "1". Therefore, switch select signals SEL1 and SEL2 attain "1". The similar operation is repeated, so that, when "111 (=7)" is input, seven output terminals 101a to 101g all output "1".
Then, a 5-bit bar graph decoder configured of more practical logic and composite gates will be described as the conventional bar graph decoder with reference to FIGS. 16 and 17. FIG. 16 is a schematic diagram showing the entire configuration of a conventional 5-bit bar graph decoder 102. Referring to FIG. 16, 5-bit bar graph decoder 102 includes 5-bit input terminals 1a to 1e, a predecoder 103 connected to input terminals 1b to 1e, a decoder 104 connected to predecoder 103 and input terminal 1a, and output terminals outputting switch select signals SEL1 to SEL32 from decoder 104.
Respective digital inputs (B5, B4, B3, B2, B1) are input to input terminals 1a to 1e. Predecoder 103 includes 15 logic gates DEC1 to DEC15 and composite gates connected to necessary ones of input terminals 1a to 1e. Decoder 104 includes 16 blocks each formed of a 2-NAND circuit and a 2-NOR circuit.
Description will now be given of operation of bar graph decoder 102 with reference to FIGS. 17A and 17B. FIG. 17A shows input data B1 to B4 input to input terminals 1b to 1e receiving data for four bits from the LSB of the 5-bit input data, and output data with respect to the input data from logic gates DEC1 to DEC15 configuring predecoder 103. FIG. 17B shows the content of digital data B5 to B1 input to input terminals 1a to 1e and switch select signals SEL1 to SEL31 output from decoder 104.
Referring to FIGS. 17A and 17B, "00000" to "11111" are input to input terminals 1a (MSB) to 1e (LSB). In response to the digital input, switch select signals SEL1 to SEL31 continuously output an enable signal. In FIG. 16, switch select signal SEL32 is an output caused by the regularity of arrangement of the same logic circuits. Switch select signal SEL32 is a dummy output, and not used practically.
When "00000 (=0)" is input for example, all the logic gates and composite gates in predecoder 103 output "1", as shown in FIG. 17A. Therefore, switch select signals from 31 output terminals all attain "0" as shown in FIG. 17B. Then, when "00001 (=1)" is input, only DEC1 which is a 4-input NOR logic gate in predecoder 103 outputs "0". Therefore, only switch select signal SEL1 attains "1". Further, when "00010 (=2)" is input, logic gates DEC1 and DEC2 in predecoder 103 output "0". Therefore, switch select signals SEL1 and SEL2 attain "1". The similar operation is repeated, so that 31 output terminals all output "1" when "11111 (=31)" is input.
The conventional bar graph decoder was configured as described above. Therefore, when an output corresponding to a 5-bit input was to be obtained for example, an assembly of two logic circuits of a predecoder and a decoder was required. Further, the predecoder was configured of logic gates and composite gates, leading to a complicated structure and a large number of elements.